UVM RAL

                                                  UVM RAL

  UVM library has the reg directory uvm-1.1b/src/reg has all the uvm ral base classes.

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       The UVM register layer classes are used to create a high-level, object-oriented model for memory-mapped registers and memories in a design under verification.
 

<         UVM register layer defines several base classes that, when properly extended, abstract the read/write operations to registers and memories in a design-under verification.
 

<         The abstraction mechanism allows verification environments and tests to be migrated from block to system levels without any modifications. Below diagram explains the test bench architecture with UVM RAL.Here spec can be in fle formats like .doc,.xl,.csr ,.ralf,.xml formats.Generator may be IDESIGNSPEC from Agnisys Inc and RALGEN from VCS , CSRCOMPILER from semifore. 




overall tb architecture