Evaluation Model
The
simulation of SystemVerilog language is based on a discrete event execution
model. Processes can be evaluated and have their own state. They are
concurrently scheduled. They are sensitive to update events. Every change of a
net or a variable generates an event (an update event). An evaluation of a
process also generates an event (an evaluation event).
Except
for events, an important aspect of the simulation is the simulation time. The
simulator maintains the time value to model the actual time in the design being
simulated. The simplest simulation time unit is called a time slot. The time
slot is divided into several regions where events can be scheduled. In
appropriate regions of a time slot different kinds of events are executed.
Dividing a time slot into ordered regions helps to provide predictable
interactions between the design and testbench code.
Regions
Observed, Reactive and Re-inactive were added to the simulation model by IEEE
1800-2005. The remaining regions correspond to the IEEE 1364-2005 simulation
model.
·
Evaluation of property expressions is executed in the Observed
region.
·
The pass/fail code from the assertion/cover action
blocks is scheduled in the Reactive region of the current time slot.
·
A #0 control
delay specified in a program block schedules the process for resumption in the
Re-inactive region.
Sampling
of signals used in sequences and properties expressions is executed in Preponed
region. Sampling of signals with #1step input
skew (see Clocking Blocks chapter) is also executed in the Preponed region.
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