SV BASICS -1:SV DATA TYPES

SystemVerilog introduces a multitude of two-valued integral data types. Having these types facilitates efficient behavioral models. These types also come handy for interface to C/C++ using Direct Programming Interface.

The following table provides a quick summary of the integral types available in SystemVerilog:

[hide]SystemVerilog Integral Data Types
Data Type	2/4 state	width	(un)signed	comments
bit	2 state	1	unsigned	may be used in bit-vector form
byte	2 state	8	signed
shortint	2 state	16	signed
int	2 state	32	signed
longint	2 state	64	signed
logic	4 state	1	unsigned	may be used in bit-vector form
reg	4 state	1	unsigned	may be used in bit-vector form
integer	4 state	32	signed
time	4 state	64	unsigned

The logic datatype

SystemVerilog introduces a new keyword logic, which can be used to declare variables as well as signals. The only constraint put on the logic datatype is that it can not be used for declaring multiply driven nets.

Additionally, SystemVerilog makes the use of reg and logic keywords (mostly) interchangeable. As a result, RTL designers may now use logic or reg for declaring most variables and signals. A wire needs to be declared only when the signal is multiply driven. This is necessitated by the fact that SystemVerilog would need a value resolution mechanism for resolving the value of the multiply driven nets and such mechanism is in place only for wire types.

VERILOG DATATYPES HOW USEFUL FOR RTL DESIGNER

Verilog-1995 standard supports variables(reg, integer and time) and signal(wire) data types. While variable data types in Verilog are four valued ('0', '1', 'Z', and 'X'), signal data types can have up to 120 values (depending on signal values and strengths).

2 VALUED DATATYPE VERSUS 4 VALUED DATATYPE

Execution time for 2 value datatypes is less as compare to 4 valued datatypes.