Sunday, August 5, 2012

CLASS IN SV
Classes in SystemVerilog are self-contained software modules. Classes are used to define higher level (abstract and concrete) types. A class can be declared in SystemVerilog using keyword class.
?
Class example and creation of objects
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
class Complex;
  local int real_;
  local int imag_;
 
  // constructor
  function new(int re_, int im_);
    real_ = re_;
    imag_ = im_;
  endfunction: new
 
  // methods
  function Complex add(Complex x, Complex y)
    Complex z;
    z = new(x.real_ + y.real_, x.imag_ + y.imag_);
    return z;
  endfunction: add
endclass: Complex
 
Complex foo = new(1.1, 2.5); // new allocates an object and foo is
                             // assigned the handle corresponding
                             // to the new object
 
Complex bar, frop;           // bar, and frop are null at this point
 
bar = foo;                   // bar copies the handle foo also holds
 
frop = bar.add(foo);         // frop is assigned a new handle which got
                             // created by invocation of new at line 14
                             // and got returned by the add method
  1. Just like C++ classes, a class in SystemVerilog constitutes attributes and methods. Attributes are data elements and are used to store the state of the class object. Methods represent the possible actions that a class may perform.
  2. Attributes might be of any user-defined or built-in type.
  3. A class method might be a class specific task or function.
  4. Attributes and methods might be declared static. See below.
  5. A class member (attribute as well as method) can be declared local or protected. A local member is visible only to the class methods. A protected member is visible to the class methods as well as other classes which inherit from the given class. By default class members are public (i.e. visible to all).
  6. A class instance may be a member of another class. This constitutes has a relationship between the two classes.
  7. A class may inherit from another class. SystemVerilog supports inheritance using keyword extends.
  8. A class may declare some members as static. Static members properties are common to all class instances.
Classes are used in behavioral modeling as well as for coding verification components. The class construct can not be synthesized (not yet) and therefor class is not a useful construct for RTL design.


No comments:

Post a Comment