What is sensitivity list in verilog?

 A simple always block runs forever it means as it touches the “end” again starts from beginning.Sensitivity list is a medium to make a controlled always block.

Example of normal always block

    always
    begin
        // statements
    end

     always @ ( sensitivity list)
      begin
           // statements
      end

The syntax of sensitivity list can be –

     A. always @ ( x or y or z)
     B. always @ ( posedge x )
     C. always @ ( posedge x or A )
     D. always @ ( posedge x or negedge y )
     E. always @ ( x, y, z)
     F. always @(*)
     G. always @*
   
The E, F and G are the new constructs added in the verilog 2001.

Usage of different syntaxes in verilog –

Point A and E are same in behavior, taking an example for syntax A and E

Example :1     Always @ ( x,y,z)
     Begin
         Sum = x + y + z
     End

Point B, C and D are normally used for sequential logic implementation

Example : 2

     always @ ( posedge clock or negedge reset )
     begin
     if (!reset)
         q<= 0;
     else
         q<= data
     end

Point F and G are equivalent in behavior. These are some easy options to use without bothering about the sensitivity list

Example : 3     Always @ (*)
     Begin
         Sum = x + y + z
     End

In this case whatever values are used in the right hand side (RHS) would be taken in the sensitivity list So there is any change in the x , y or z values, the always block would be executed..