why we making an interface as virtual

An instance of a SV Interface (like module in Verilog) is a static object which shall be created during elaboration which is alive throught-out the course of the simulation.
Where as a class object is dynamic which can be allocated memory and can be freed during the course of simulation. So, we cannot instantiate any static objects (let it be interfaces or modules) inside the class.
For that reason, a physical interface is assigned to a virtual interface defined (which is just a handle) inside a monitor/driver class through which you can access the real interface signals.