Using event based modeling in verilog to avoid Racing between always blocks.

In most of our designs, we have to perform some operation on the posedge of clock. To implement this, we normally use different always block with the posedge of clock in the sensitivity list.

Some times, we need to use the signal in one always block, which is getting assigned a value from another, and here the actual problem starts.

Since the all the always blocks execute concurrently in the design, which may create racing between signals, which is again varies among simulator to simulator.

For this scenario, the signals may get value from one always block before/after it is used in another one.

Using “event” in the verilog programming can be one way to take care this kind of situation.

Example 1 :

Here two always blocks are shown,

In this case we are trying to set some modes by looking into some conditions. Also, we want to use the modes at the posedge of clock and perform some other operation.

Since both always blockes are working at the same posedge of clock, which may create a racing between the mode signals.

This is a small example but in real-time scenario, it might be more complex and big.

It may take the new value of mode of continue with the older value, depends on the simulator’s algorithm.

Block – 1 :

always (posedge clock)
begin
    if (condition1)
        mode1 = 1′b1;
    else if (condition2)
        mode2 = 1′b1;
    else
        mode3 = 1′b0;
end

Block – 2 :

always (posedge clock)
begin
    if( mode1 && conditions3)
        output <= input1;
    else if (mode2 && condition4)
        output <= input2
    else
        output <= 2′b0;
end

Now, Lets try to avoid the racing between these two always blocks.

Here, we use an “event” to trigger the other always block, and the triggering will take place at the last of first always block.

Since we wanted to run the both always block at the posedge of the clock, which is also happening here.

By using the event in the sensitivity list of other always block makes sure that this block will execute when the first will be completed, and it will be able to use the new values assigned to the mode variables.

We can have multiple events in the design.

// event declaration
event ev_mode

Block – 1 :

always (posedge clock)
begin
    if (condition1)
        mode1 = 1′b1;
    else if (condition2)
        mode2 = 1′b1;
    else
        mode3 = 1′b0;
    -> ev_mode
end

Block – 2 :

always (ev_mode)
begin
    if( mode1 && conditions3)
        output <= input1;
    else if (mode2 && condition4)
        output <= input2
    else
        output <= 2′b0;
end

Design synthesis and relevant verilog code for DFF

---------Basic componet of RTL Synthesis

For RTL Coding, one should know that what code will infer which hardware in the design and vise versa.

The Design engineer should be aware of relevant code and the output logic so he can be able to minimize the design and the no of gates using.

In this post we will see deferent DFF and their verilog codes

DFF ( D- Flip-Flop)

reg q;

always @ (posedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the posegde of the clock and it will remain untouched till next posedge of the clock since the q is defined as reg.

D-Flip Flop

DFF ( D- Flip-Flop) with Asynchronous reset.

reg q;

always @ (posedge clk or posedge reset)
if (reset)
q <= 1′b0;
else
q <= d;

According to above code, the reset is positive edge triggered and asynchronous so it is kept in the sensitivity list of always block with the posedge.

Inside the always block, there are a conditional statement to check whether the reset is true (1), otherwise it behaves as normal DFF

DFF - Async Reset

DFF ( D- Flip-Flop) with synchronous reset

reg q;

always @ (posedge clk)
if (reset)
q <= 1′b0;
else
q <= d;

Synchronous reset means the flop will be reset only with the posedge of clock, hence the sensitivity list does not have the reset signal; However it check the reset for true whenever the posedg of clock comes.

DFF - Sync Reset

DFF ( D- Flip-Flop) with gated clock.

reg q;
wire gtd_clk = enable && clk;

always @ (posedge gtd_clk)
q <= d;

Many times it becomes required to apply clock to the design only when the enable is active. This is done by the gated clock. The clock and enable both are the inputs to a and gate and the output of the gate goes to the clock input of the flop.

DFF - Gated Clock

Data Enabled DFF

reg q;

always @ (posedge clk)
if (enable)
q <= d;

Data Enabled flops has a mux at the data input, which is controlled by the enable signal. Now even the posedge of clock comes to the flop, flop will not change the value until enable is not active.

DFF - Data Enable

Negative Edge triggered DFF

reg q;

always @ (negedge clk)
q <= d;

In this code, the value of D(data) will be assigned to output (q) at the negedge of the clock and it will remain untouched till next negedge of the clock since the q is defined as reg.

DFF -Negative Edge

What is Timescale in verilog codes

The ‘timescale is one of the compiler directive to specify the unit for the delays used in the design with their precision.

The timescale line is very important in the verilog simulation, because there are no any default delays specified by the verilog.

Syntax :

`timescale <time unit>/<time precision>

Here :

time unit : This is the time to be used as one unit for all the delays used in the design.

time precision : This represents the minimum delay which needs to be considered during simulation or it decides that how many decimal point would be used with the time unit.

Range of Timescale :

The range for time unit can be from seconds to femto-seconds, which includes all the time units including s (second), ms(mili-second), us(micro-second), ns(nano-second), ps(pico-second) and fs(femto-second).

Example :

`timescale 1ns/1ps

Here :

1ps = 0.001 ns

#1; // = 1ns delay

#1.003; // = will be considered as a valid delay

#1.0009; // = will be taken as 1 ns only since it is out of the precision value.

What are sequential and parallel blocks, what is fork and join statements? How it is deffer than begin and end?

In verilog, we have two types of block – sequential blocks and parallel blocks. Lets look into both blocks one by one

1. Sequential Blocks –

In the sequential blocks, begin and end keywords are used to group the statements, All the statement in this group executes sequentially. ( this rule is not applicable for nonblocking assignments). If the statements are given with some timing/delays then the given delays get added into. It would be clearer with following examples.

Example -1 -

reg a,b,c;
initial
begin
     a = 1′b1;
     b = 1′b0;
     c = 1′b1;
end
The Example -1 is showing the sequential block without delays, All the statements written inside the begin-end will execute sequentially and after the execution of initial block, final values are a=1, b=0 and c=1

Example -2 -

reg a,b,c;
initial
begin
     #5 a = 1′b1;
     #10 b = 1′b0;
     #15 c = 1′b1;
end

The Example -2 is showing the sequential block with delays, In this case, the same statements are given with some delays, Since All the statements execute sequentially, the a will get value 1 after 5 time unit, b gets value after 15 time unit and c will take value 1 after 30 time unit

2. parallel Blocks –

The statements written inside the parallel block, execute parallel, If the sequencing is required then it can be given by providing some delays before the statements. In parallel blocks, all the statements occur within fork and join

Example -3 -

reg a,b,c;
initial
fork
     #5 a = 1′b1;
     #10 b = 1′b0;
     #15 c = 1′b1;
join

Form Example -3, all the statements written inside the fork and join, executes parallel, it means the c with have value ‘1′ after 15 time unit, in case of sequential blocks it was 30 time unit ( example 2)

The fork and join statements can be nested with begin-end

Example -4 ( Nested block)

reg a,b,c,d;
initial
begin
fork
     #5 a = 1′b1;
     #10 b = 1′b0;
     #15 c = 1′b1;
join

1. 30 d = 1′b0;

end

From Example -4, the initial block contains begin-end and fork-join both. In this case c takes value after 15 time unit, and d takes the value after 30 time unit.

What is sensitivity list in verilog?

 A simple always block runs forever it means as it touches the “end” again starts from beginning.Sensitivity list is a medium to make a controlled always block.

Example of normal always block

    always
    begin
        // statements
    end

     always @ ( sensitivity list)
      begin
           // statements
      end

The syntax of sensitivity list can be –

     A. always @ ( x or y or z)
     B. always @ ( posedge x )
     C. always @ ( posedge x or A )
     D. always @ ( posedge x or negedge y )
     E. always @ ( x, y, z)
     F. always @(*)
     G. always @*
   
The E, F and G are the new constructs added in the verilog 2001.

Usage of different syntaxes in verilog –

Point A and E are same in behavior, taking an example for syntax A and E

Example :1     Always @ ( x,y,z)
     Begin
         Sum = x + y + z
     End

Point B, C and D are normally used for sequential logic implementation

Example : 2

     always @ ( posedge clock or negedge reset )
     begin
     if (!reset)
         q<= 0;
     else
         q<= data
     end

Point F and G are equivalent in behavior. These are some easy options to use without bothering about the sensitivity list

Example : 3     Always @ (*)
     Begin
         Sum = x + y + z
     End

In this case whatever values are used in the right hand side (RHS) would be taken in the sensitivity list So there is any change in the x , y or z values, the always block would be executed..
 

What is the difference between a function and a task? in verilog

1. behavior –

Function : function call happens in real time OR no simulation delay can be inserted during the function call

Task : Tasks can be inserted with a delay

1. No of outputs :

Function : A function can have at least one input arg to be passed, and also it can have only one output to drive

Task : Task can have any no of inputs and outputs.

1. Nesting :

Function : A function can call a function inside it but not a task

Task : Task can call either a function or a task inside it.

1. Synthesis :

Function : A function can be synthesized

Task : Tasks are not synthesizable

1. Limitations :

Function : A function does not allow any delay, timing, event inside it

Task : Tasks can have delays, events inside it

1. Usage :

Function : A can be used for RTL as well as behavioral coding ( mostly for combinational logic)

Task : Tasks can be used for behavioral modeling only.

What is the difference between blocking and nonblocking statements in verilog

In verilog, we have two types of assignment operators i.e. blocking (=) and non- blocking (<=). These two have theirs special usages – Here are the differences

1. behavior  –

The blocking statements are as similar as any sequential programming language. In short, they execute sequentially.

The non-blocking statements are executed concurrently; it means if five statements are written together then it would depend on the simulator to execute which statement first. Ideally all the statements should execute at the same time.

1. Synthesis –

The blocking statements infer simple “connection OR wire” during the synthesis,

Non-blocking statements infer Flop/latch.

1. Usage -

The blocking statements are used normally for combinational logic implementation OR whenever the synchronization/sequence required between the assignments,

Non blocking statements are used for sequential implementation

Universal Logic : Mux to Logic gates conversion

In this post, we will see haw a 2:1 MUX can be used to create different logic gates.

1. Designing an Inverter using 2:1 MUX.

To design an inverter using 2:1 mux, we have to use the input as the select line of the MUX and the “zeroth” select line would be tied with “Logic 1 ” and “First” select line would be tired with “Logic 0″, Now when the select line (Input) goes to “1″ the out put will be “0″ ( inverted).

Image : MUX to inverter -

2:1 mux as an inverter

2. Designing an AND Gate using 2:1 MUX.

To design an AND using 2:1 mux, we need to tie the “zeroth” input to “Logic 0″ and the “First” input to the one of the input of the AND Gate. The other input of AND gate would be connected with the select line of the MUX.

Now, the out put of the MUX would be “1″ only if the both of the inputs are “1″ otherwise it would be “0″ for all conditions.

Image : MUX to AND Gate -

2:1 MUX as an AND gate

3. Designing an OR Gate using 2:1 MUX.

To design an OR using 2:1 mux, we need to tie the “First” input to “Logic 1″ and the “Zeroth” input to the one of the input of the OR Gate. The other input of OR gate would be connected with the select line of the MUX.

Now, the output of the MUX would be “1″ when any oth the two inputs would be “1″ otherwise it would be “0″ for all conditions.

Image : MUX to OR Gate -

2:1 MUX as an OR Gate

4. Designing an NOR Gate using 2:1 MUX.

To design the NOR using 2:1 mux, we need to tie the “Zeroth” input of mux to one of the input of NOR and another input of MUX is tied to “0″ . The another input of NOR gate would be applied to the select line of the MUX.

Now, the output of the MUX would be A’B’ = (A+B)’. which is as same as the output of NOR Gate.

Image : MUX to NOR Gate -

2:1 mux as a NOR Gate

5. Designing an NAND Gate using 2:1 MUX.

To design the NAND using 2:1 mux, we need to combine the AND Gate and inverter implementation

6. Designing an XOR Gate using 2:1 MUX.

To design the XOR using 2:1 mux, we need to tie the “Zeroth” input of mux to one of the input of XOR and another input of MUX to the inverted of first input. The another input of XOR gate would be applied to the select line of the MUX.

Now, the output of the MUX would be AB’ + A’B which is as same as the output of XOR Gate.

Image : MUX to XOR Gate -

2:1 Mux as a XOR gate

7. Designing an XNOR Gate using 2:1 MUX.

To design the XNOR using 2:1 mux, we need to tie the “First” input of mux to one of the input of XOR and another input of MUX to the inverted of first input. The another input of XOR gate would be applied to the select line of the MUX.

Now, the output of the MUX would be A’B’ + AB which is as same as the output of XNOR Gate.

Image : MUX to XNOR Gate -

2:1 mux as a XNOR Gate

CLASS IN SV

Classes in SystemVerilog are self-contained software modules. Classes are used to define higher level (abstract and concrete) types. A class can be declared in SystemVerilog using keyword class.

?

Class example and creation of objects

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

class Complex;   local int real_;   local int imag_;     // constructor   function new(int re_, int im_);     real_ = re_;     imag_ = im_;   endfunction: new     // methods   function Complex add(Complex x, Complex y)     Complex z;     z = new(x.real_ + y.real_, x.imag_ + y.imag_);     return z;   endfunction: add endclass: Complex   Complex foo = new(1.1, 2.5); // new allocates an object and foo is                              // assigned the handle corresponding                              // to the new object   Complex bar, frop;           // bar, and frop are null at this point   bar = foo;                   // bar copies the handle foo also holds   frop = bar.add(foo);         // frop is assigned a new handle which got                              // created by invocation of new at line 14                              // and got returned by the add method

1. Just like C++ classes, a class in SystemVerilog constitutes attributes and methods. Attributes are data elements and are used to store the state of the class object. Methods represent the possible actions that a class may perform.
2. Attributes might be of any user-defined or built-in type.
3. A class method might be a class specific task or function.
4. Attributes and methods might be declared static. See below.
5. A class member (attribute as well as method) can be declared local or protected. A local member is visible only to the class methods. A protected member is visible to the class methods as well as other classes which inherit from the given class. By default class members are public (i.e. visible to all).
6. A class instance may be a member of another class. This constitutes has a relationship between the two classes.
7. A class may inherit from another class. SystemVerilog supports inheritance using keyword extends.
8. A class may declare some members as static. Static members properties are common to all class instances.

Classes are used in behavioral modeling as well as for coding verification components. The class construct can not be synthesized (not yet) and therefor class is not a useful construct for RTL design.